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Table 5-1 · PCI Bus Interface Signals (Continued)
Name
Type
Used
On
Description
Active low output from the Target indicating that it is capable of transferring data on the full
ACK64N
Bidirectional (STS)
64
64-bit PCI bus. This signal is driven in response to the REQ64N signal and has the same
timing as DEVSELN. This signal is not required in 32-bit PCI systems.
Active high signal indicating that the core supports 66 MHz operation. This output will be
driven LOW if the MHZ_66 parameter is NOT set. When it is set, the output is tristated.
M66EN
Bidirectional (OD)
All
If hot-swap is enabled, this is also used as an input to verify the PCI clock frequency during
hot-swap insertion cycles. The M66EN PCI signal pin should be pulled up with a 5 k Ω
resistor.
Note:
Active low signals are designated with a trailing uppercase N .
Backend System-Level Signals
CorePCIF buffers the PCI clock and reset internally onto global networks. The outputs shown in Table 5-2 allow these
global networks to be used for additional user backend logic.
Table 5-2 · System-Level Signals
Name
Type
Width
Description
Clock output. The core uses an internal clock buffer. This is the buffered version of the clock
CLK_OUT
Output
1
and should be used for clocking any other logic in the FPGA that is clocked by the PCI clock
(see “Clocking” on page 127 ).
When the GENERATE_PCICLK parameter is set, this input is used to drive the PCI clock
CLK_IN
Input
1
output, and also clocks the internal core logic. CLK_OUT should be used to clock additional
logic inside the FPGA (see “Clocking” on page 127 ).
Reset output. This is a buffered version of the PCI reset. If USE_GLOBAL_RESET = 1, a
global buffer drives the internal reset network in the core as well as this reset output. If
RST_OUTN
Output
1
USE_GLOBAL_RESET = 0, a buffer tree is created and a reset output from the tree is fed to
the reset output. RST_OUTN should be used for resetting any other logic in the FPGA.
If the hot-swap function is enabled, this reset will also be asserted during a hot-swap insertion
or extraction cycle per the Hot-Swap Specification.
FRAMEN_OUT
IRDYN_OUT
Output
Output
1
1
Buffered version of the PCI FRAMEN signal intended for connection to a PCI arbiter. Care
must be exercised when using this output to avoid causing PCI setup timing issues.
Buffered version of the PCI IRDYN signal intended for connection to a PCI arbiter. Care must
be exercised when using this output to avoid causing PCI setup timing issues.
Buffered version of the PCI SERRN signal. Allows the backend logic to know whether
SERRN_OUT
Output
1
SERRN has been asserted. Care must be exercised when using this output to avoid causing PCI
setup timing issues.
CFG_STATUS
44
Output
16
Provides the current value of the PCI configuration status register ( Table 7-7 on page 109 ).
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